Math Editor

Logic 2 Problems

(1) Design the sequential circuit for the state diagram shown in the figure, use D flip flops.

DA=X

DB=BX

Y=AB

(4) Design digital system with 3 registers A, B, C and a flip flop E (of J-K type) to perform the following:

• When a start signal S=1, Transfer two numbers to A and B.
  • If A > B: Clear register A and set flip flop E to 1, then increment B in the next clock pulse. Then system stops.
    • • • • 1. If A <= B: Clear flip flop E, then,
            2. If A < B shift left A, then add the contents of A (after shift) to B and transfer results to C. Then system stops.
            3. If A = B: increment B in the next clock pulse, then system stops

circuit realization

(6) A building consists of 4 stages with an underground stage

it's needed to design the counter circuit for its lifter:

• Draw the required state diagram for the counter.
• Design the counter circuit using JK flip flop.

flip flop C will flip in all cases except A'B'C'X' OR AB'C'X

JC=KC=A′B′C′X′norAB′C′X

flip flop B will flip in four cases: A'B'CX + A'BCX' + A'BCX + AB'C'X'

JB=KB=A′B′CX+A′BC′X′+A′BCX+AB′C′X′

flip flop A will flip in two cases: A'BCX + AB'C'X'

JA=KA=A′BCX+AB′C′X'

JK Excitation table

JA=BCX

KA=X'

JB=CX

KB=AB'X

JC=B+A'X+AX'

KC=1

(4) for the following ripple counter, find:

• The count sequence.
• Is the counter self-starting?

A and C always work

B works when C flips to zero

JA=B KA=1

JB=A'C KB=1

JC=1 KC=A'

COUNT SEQUENCE: 1 2 7 3 4

UNUSED STATES: 5 => 1 6 => 3 #SELF STARTI

(3) Design a counter with the following sequence: 2, 3, 5, 6, 7 (using T- flip flop)

TA=BC

TB=B'+A'C

TC=A+C'